An integrated circuit device is manufactured based on a physical design which describes how the device has to be built up. Integrated circuit devices are stacks of layers of different materials. Each layer locally comprises features of the material, such as metal wires in a metal layer, or locally comprises an adapted material, such as a locally created p-diffusion in an n-well area in a semiconductor material for manufacturing a pmos transistor. The integrated circuit layout geometrically describes where the features have to be created or where the material has to be adapted. The layout is the basis for manufacturing a plurality of masks which are used in a lithographical process to manufacture the design of the layout on the semiconductor device. See, for example, patent application US2003/192013, which discusses how the physical layout is adapted to manufacture a plurality of masks and how the masks are used to manufacture the layers of the semiconductor device.
Nowadays, the features of the integrated circuit become very small and, in general, they are difficult to manufacture on the integrated circuit device. Some patterns are very difficult to manufacture and must, for example, be avoided, or have to be adapted to a less difficult manufacturable pattern.
Traditionally, see for example patent U.S. Pat. No. 6,189,132 and patent application US2003/009728, the prevention of manufacturability problems was based on enforcing minimal distances between the features of the integrated circuit and enforcing minimal spaces between the features. Tools which were used to enforce the minimal distances were able to detect instances of widths of the features and instances of spaces between the features.
In other tools, a geometrical description of a relative complex pattern is provided to a pattern matching tool which is only capable of finding exact copies of the pattern in the physical layout, which means that only instances of the pattern which have exactly the same size are found. However, variations of the geometrically described pattern may also have manufacturability problems.
Without being bound to an exact geometry, relatively complex patterns may be specified with SVRF of Mentor Graphics. SVRF stands for Standard Verification Rule Format. SVRF is a language for specifying violations against design rules in a layout. If a design rule is specified, a Mentor Graphics tool is used to execute the algorithm and detect violations of the design rule in a physical layout. The specification of the design rule is achieved by means of algorithms that compute error layers for each fault situation. It is up to the implementer of a design rule to develop these algorithms. The algorithms are written using operations on layers of the physical layout, or selecting edges or shapes of layout features. For more complex patterns this quickly leads to hard-to-write and hard-to-read design rule descriptions and consequently they are hard to maintain and hard to debug. Thus, SVRF is not a user-friendly solution for defining certain complex patterns. Further, some complex patterns can not be described in SVRF.